Microcode review (mechanical pass) — 2026-09-29¶

Generated by tools/ucode_review.py from firmware/microcode/ucode-generator2/test.hex. Rules are in the script's docstring; the hardware model behind them is the one used for docs/isa/ (pipeline registers apply a step's word for the whole step, memory writes happen while -MEM-WR is low, the address bus follows the register selected by ADDR-REG-ID). Register families are checked on every member (all 256 records that hold microcode).

Totals by rule: L1 8, R2 3, S1 107

Opcode	Mnemonic	Steps	Findings
$00	START	4	clean
$01	ON	5	S1 x1
$02	OFF	5	S1 x1
$03	HALT	5	clean
$04	JSR	28	S1 x1
$05	RET	17	S1 x2
$06	JSRUR	30	S1 x1
$07	PUSHR	26	S1 x2
$08	POPR	24	S1 x1
$09	PUSH	12	clean
$0A	POP	10	S1 x1
$0B	MVAT	7	clean
$0C	MVTA	8	clean
$0D	LDTI	9	clean
$0E	LDAI	10	clean
$0F	MOVRR	14	R2 x3, S1 x1
$10	MVIB	10	clean
$11	MVIB R1	10	clean
$12	MVIB R2	10	clean
$13	MVIB R3	10	clean
$14	MVIB R4	10	clean
$15	MVIB R5	10	clean
$16	MVIB R6	10	clean
$17	MVIB R7	10	clean
$18	MVIW	15	clean
$19	MVIW R1	15	clean
$1A	MVIW R2	15	clean
$1B	MVIW R3	15	clean
$1C	MVIW R4	15	clean
$1D	MVIW R5	15	clean
$1E	MVIW R6	15	clean
$1F	MVIW R7	15	clean
$20	MVRLA	7	clean
$21	MVRLA R1	8	S1 x1
$22	MVRLA R2	8	S1 x1
$23	MVRLA R3	8	S1 x1
$24	MVRLA R4	8	S1 x1
$25	MVRLA R5	8	S1 x1
$26	MVRLA R6	8	S1 x1
$27	MVRLA R7	8	S1 x1
$28	MVRHA	7	clean
$29	MVRHA R1	8	S1 x1
$2A	MVRHA R2	8	S1 x1
$2B	MVRHA R3	8	S1 x1
$2C	MVRHA R4	8	S1 x1
$2D	MVRHA R5	8	S1 x1
$2E	MVRHA R6	8	S1 x1
$2F	MVRHA R7	8	S1 x1
$30	MVARL	9	clean
$31	MVARL R1	9	clean
$32	MVARL R2	9	clean
$33	MVARL R3	9	clean
$34	MVARL R4	9	clean
$35	MVARL R5	9	clean
$36	MVARL R6	9	clean
$37	MVARL R7	9	clean
$38	MVARH	9	clean
$39	MVARH R1	9	clean
$3A	MVARH R2	9	clean
$3B	MVARH R3	9	clean
$3C	MVARH R4	9	clean
$3D	MVARH R5	9	clean
$3E	MVARH R6	9	clean
$3F	MVARH R7	9	clean
$40	LDAVR	8	clean
$41	LDAVR R1	8	clean
$42	LDAVR R2	8	clean
$43	LDAVR R3	8	clean
$44	LDAVR R4	8	clean
$45	LDAVR R5	8	clean
$46	LDAVR R6	8	clean
$47	LDAVR R7	8	clean
$48	STAVR	9	clean
$49	STAVR R1	9	clean
$4A	STAVR R2	9	clean
$4B	STAVR R3	9	clean
$4C	STAVR R4	9	clean
$4D	STAVR R5	9	clean
$4E	STAVR R6	9	clean
$4F	STAVR R7	9	clean
$50	INCR	6	S1 x1
$51	INCR R1	6	S1 x1
$52	INCR R2	6	S1 x1
$53	INCR R3	6	S1 x1
$54	INCR R4	6	S1 x1
$55	INCR R5	6	S1 x1
$56	INCR R6	6	S1 x1
$57	INCR R7	6	S1 x1
$58	DECR	6	clean
$59	DECR R1	7	S1 x1
$5A	DECR R2	7	S1 x1
$5B	DECR R3	7	S1 x1
$5C	DECR R4	7	S1 x1
$5D	DECR R5	7	S1 x1
$5E	DECR R6	7	S1 x1
$5F	DECR R7	7	S1 x1
$60	OUTA	9	clean
$61	OP61	9	clean
$62	OP62	9	clean
$63	OP63	9	clean
$64	OP64	9	clean
$65	OP65	9	clean
$66	OP66	9	clean
$67	OP67	9	clean
$68	OP68	9	clean
$69	OP69	9	clean
$6A	OP6A	9	clean
$6B	OP6B	9	clean
$6C	OP6C	9	clean
$6D	OP6D	9	clean
$6E	OP6E	9	clean
$6F	OP6F	9	clean
$70	OUTI	10	clean
$71	OP71	11	clean
$72	OP72	11	clean
$73	OP73	11	clean
$74	OP74	11	clean
$75	OP75	11	clean
$76	OP76	11	clean
$77	OP77	11	clean
$78	OP78	11	clean
$79	OP79	11	clean
$7A	OP7A	11	clean
$7B	OP7B	11	clean
$7C	OP7C	11	clean
$7D	OP7D	11	clean
$7E	OP7E	11	clean
$7F	OP7F	11	clean
$80	LDZ	26	S1 x2
$81	LDZ R1	26	S1 x2
$82	LDZ R2	26	S1 x2
$83	LDZ R3	26	S1 x2
$84	LDZ R4	26	S1 x2
$85	LDZ R5	26	S1 x2
$86	LDZ R6	26	S1 x2
$87	LDZ R7	26	S1 x2
$88	STZ	27	S1 x2
$89	STZ R1	28	S1 x3
$8A	STZ R2	27	S1 x3
$8B	STZ R3	28	S1 x3
$8C	STZ R4	28	S1 x3
$8D	STZ R5	28	S1 x3
$8E	STZ R6	28	S1 x3
$8F	STZ R7	28	S1 x3
$90	INP	9	clean
$91	OP91	9	clean
$92	OP92	9	clean
$93	OP93	9	clean
$94	OP94	9	clean
$95	OP95	9	clean
$96	OP96	9	clean
$97	OP97	9	clean
$98	OP98	9	clean
$99	OP99	9	clean
$9A	OP9A	9	clean
$9B	OP9B	9	clean
$9C	OP9C	9	clean
$9D	OP9D	9	clean
$9E	OP9E	9	clean
$9F	OP9F	9	clean
$A0	BR	18	clean
$A1	BRZ	18	clean
$A2	BRNZ	18	clean
$A3	BRINH	18	clean
$A4	BRINL	18	clean
$A5	BRNC	5	clean
$A6	BRC	18	clean
$A7	BRLT	18	clean
$A8	BREQ	18	clean
$A9	BRGT	18	clean
$AA	BRNEQ	18	clean
$AB	BR16Z	18	clean
$AC	BR16NZ	18	clean
$AD	BRUR	18	S1 x1
$AE	OPAE	5	clean
$AF	BRDEV	18	clean
$B0	ADDI	12	clean
$B1	SUBI	12	clean
$B2	ORI	10	clean
$B3	ANDI	10	clean
$B4	XORI	10	clean
$B5	INVA	7	clean
$B6	SHL	13	L1 x1
$B7	SHR	13	L1 x1
$B8	ADDT	10	clean
$B9	SUBT	10	clean
$BA	ORT	8	clean
$BB	ANDT	8	clean
$BC	XORT	8	clean
$BD	RSHL	12	L1 x1
$BE	RSHR	13	L1 x1
$BF	PSHR	13	L1 x1
$C0	ADDIW	42	clean
$C1	ADDIW R1	43	S1 x1
$C2	ADDIW R2	43	S1 x1
$C3	ADDIW R3	43	S1 x1
$C4	ADDIW R4	43	S1 x1
$C5	ADDIW R5	43	S1 x1
$C6	ADDIW R6	43	S1 x1
$C7	ADDIW R7	43	S1 x1
$C8	SHL16	32	clean
$C9	SHL16 R1	33	S1 x1
$CA	SHL16 R2	33	S1 x1
$CB	SHL16 R3	33	S1 x1
$CC	SHL16 R4	33	S1 x1
$CD	SHL16 R5	33	S1 x1
$CE	SHL16 R6	33	S1 x1
$CF	SHL16 R7	33	S1 x1
$D0	LDIVR	11	clean
$D1	LDIVR R1	11	clean
$D2	LDIVR R2	11	clean
$D3	LDIVR R3	11	clean
$D4	LDIVR R4	11	clean
$D5	LDIVR R5	11	clean
$D6	LDIVR R6	11	clean
$D7	LDIVR R7	11	clean
$D8	BRVR	18	clean
$D9	BRVR R1	18	clean
$DA	BRVR R2	18	clean
$DB	BRVR R3	18	clean
$DC	BRVR R4	18	clean
$DD	BRVR R5	18	clean
$DE	BRVR R6	18	clean
$DF	BRVR R7	18	clean
$E0	CSHL	13	L1 x1
$E1	CSHR	13	L1 x1
$E2	ADDIC	12	clean
$E3	ADDTC	10	clean
$E4	LDA	18	clean
$E5	STA	19	clean
$E6	LDT	17	clean
$E7	STT	17	clean
$E8	STR	28	clean
$E9	STR R1	29	S1 x1
$EA	STR R2	28	S1 x1
$EB	STR R3	29	S1 x1
$EC	STR R4	29	S1 x1
$ED	STR R5	29	S1 x1
$EE	STR R6	29	S1 x1
$EF	STR R7	29	S1 x1
$F0	LDR	26	clean
$F1	LDR R1	26	clean
$F2	LDR R2	26	clean
$F3	LDR R3	26	clean
$F4	LDR R4	26	clean
$F5	LDR R5	26	clean
$F6	LDR R6	26	clean
$F7	LDR R7	26	clean
$F8	OPF8	5	clean
$F9	OPF9	5	clean
$FA	OPFA	5	clean
$FB	INTE	6	S1 x1
$FC	INTD	6	S1 x1
$FD	IRET	19	S1 x2
$FE	IADDR	13	clean
$FF	INT	26	L1 x1, S1 x2

Details (idle steps S1 listed as counts only)¶

$01 ON (5 steps) idle steps: [3]¶

$02 OFF (5 steps) idle steps: [3]¶

$04 JSR (28 steps) idle steps: [22]¶

$05 RET (17 steps) idle steps: [3, 12]¶

$06 JSRUR (30 steps) idle steps: [25]¶

$07 PUSHR (26 steps) idle steps: [7, 16]¶

$08 POPR (24 steps) idle steps: [7]¶

$0A POP (10 steps) idle steps: [3]¶

$0F MOVRR (14 steps) idle steps: [7]¶

R2 step 9: several data-bus drivers at once: ['-REG-RD-LO', '-REG-RD-HI']
R2 step 10: several data-bus drivers at once: ['-REG-RD-LO', '-REG-RD-HI']
R2 step 11: several data-bus drivers at once: ['-REG-RD-LO', '-REG-RD-HI']

$21 MVRLA R1 (8 steps) idle steps: [3]¶

$22 MVRLA R2 (8 steps) idle steps: [3]¶

$23 MVRLA R3 (8 steps) idle steps: [3]¶

$24 MVRLA R4 (8 steps) idle steps: [3]¶

$25 MVRLA R5 (8 steps) idle steps: [3]¶

$26 MVRLA R6 (8 steps) idle steps: [3]¶

$27 MVRLA R7 (8 steps) idle steps: [3]¶

$29 MVRHA R1 (8 steps) idle steps: [3]¶

$2A MVRHA R2 (8 steps) idle steps: [3]¶

$2B MVRHA R3 (8 steps) idle steps: [3]¶

$2C MVRHA R4 (8 steps) idle steps: [3]¶

$2D MVRHA R5 (8 steps) idle steps: [3]¶

$2E MVRHA R6 (8 steps) idle steps: [3]¶

$2F MVRHA R7 (8 steps) idle steps: [3]¶

$50 INCR (6 steps) idle steps: [3]¶

$51 INCR R1 (6 steps) idle steps: [3]¶

$52 INCR R2 (6 steps) idle steps: [3]¶

$53 INCR R3 (6 steps) idle steps: [3]¶

$54 INCR R4 (6 steps) idle steps: [3]¶

$55 INCR R5 (6 steps) idle steps: [3]¶

$56 INCR R6 (6 steps) idle steps: [3]¶

$57 INCR R7 (6 steps) idle steps: [3]¶

$59 DECR R1 (7 steps) idle steps: [3]¶

$5A DECR R2 (7 steps) idle steps: [3]¶

$5B DECR R3 (7 steps) idle steps: [3]¶

$5C DECR R4 (7 steps) idle steps: [3]¶

$5D DECR R5 (7 steps) idle steps: [3]¶

$5E DECR R6 (7 steps) idle steps: [3]¶

$5F DECR R7 (7 steps) idle steps: [3]¶

$80 LDZ (26 steps) idle steps: [3, 11]¶

$81 LDZ R1 (26 steps) idle steps: [3, 11]¶

$82 LDZ R2 (26 steps) idle steps: [3, 11]¶

$83 LDZ R3 (26 steps) idle steps: [3, 11]¶

$84 LDZ R4 (26 steps) idle steps: [3, 11]¶

$85 LDZ R5 (26 steps) idle steps: [3, 11]¶

$86 LDZ R6 (26 steps) idle steps: [3, 11]¶

$87 LDZ R7 (26 steps) idle steps: [3, 11]¶

$88 STZ (27 steps) idle steps: [3, 11]¶

$89 STZ R1 (28 steps) idle steps: [3, 11, 13]¶

$8A STZ R2 (27 steps) idle steps: [3, 11, 13]¶

$8B STZ R3 (28 steps) idle steps: [3, 11, 13]¶

$8C STZ R4 (28 steps) idle steps: [3, 11, 13]¶

$8D STZ R5 (28 steps) idle steps: [3, 11, 13]¶

$8E STZ R6 (28 steps) idle steps: [3, 11, 13]¶

$8F STZ R7 (28 steps) idle steps: [3, 11, 13]¶

$AD BRUR (18 steps) idle steps: [13]¶

$B6 SHL (13 steps)¶

L1 step 10: load ['-AC-LD'] with nothing driving the data bus

$B7 SHR (13 steps)¶

L1 step 10: load ['-AC-LD'] with nothing driving the data bus

$BD RSHL (12 steps)¶

L1 step 9: load ['-AC-LD'] with nothing driving the data bus

$BE RSHR (13 steps)¶

L1 step 10: load ['-AC-LD'] with nothing driving the data bus

$BF PSHR (13 steps)¶

L1 step 10: load ['-AC-LD'] with nothing driving the data bus

$C1 ADDIW R1 (43 steps) idle steps: [7]¶

$C2 ADDIW R2 (43 steps) idle steps: [7]¶

$C3 ADDIW R3 (43 steps) idle steps: [7]¶

$C4 ADDIW R4 (43 steps) idle steps: [7]¶

$C5 ADDIW R5 (43 steps) idle steps: [7]¶

$C6 ADDIW R6 (43 steps) idle steps: [7]¶

$C7 ADDIW R7 (43 steps) idle steps: [7]¶

$C9 SHL16 R1 (33 steps) idle steps: [3]¶

$CA SHL16 R2 (33 steps) idle steps: [3]¶

$CB SHL16 R3 (33 steps) idle steps: [3]¶

$CC SHL16 R4 (33 steps) idle steps: [3]¶

$CD SHL16 R5 (33 steps) idle steps: [3]¶

$CE SHL16 R6 (33 steps) idle steps: [3]¶

$CF SHL16 R7 (33 steps) idle steps: [3]¶

$E0 CSHL (13 steps)¶

L1 step 10: load ['-AC-LD'] with nothing driving the data bus

$E1 CSHR (13 steps)¶

L1 step 10: load ['-AC-LD'] with nothing driving the data bus

$E9 STR R1 (29 steps) idle steps: [14]¶

$EA STR R2 (28 steps) idle steps: [14]¶

$EB STR R3 (29 steps) idle steps: [14]¶

$EC STR R4 (29 steps) idle steps: [14]¶

$ED STR R5 (29 steps) idle steps: [14]¶

$EE STR R6 (29 steps) idle steps: [14]¶

$EF STR R7 (29 steps) idle steps: [14]¶

$FB INTE (6 steps) idle steps: [4]¶

$FC INTD (6 steps) idle steps: [4]¶

$FD IRET (19 steps) idle steps: [3, 12]¶

$FF INT (26 steps) idle steps: [4, 20]¶

L1 step 23: load ['REG-LD-LO', 'REG-LD-HI'] with nothing driving the data bus