YACC1 ISA timing diagrams¶
Generated by tools/ucode_wavedrom.py --all (make isa) from the microcode image firmware/microcode/ucode-generator2/test.hex and the signal table firmware/microcode/yaccsignaldata2.h: one WaveDrom diagram per opcode defined in firmware/opcodes.h, control levels per microcode step plus the bus behaviour from an ASSUMED typical-LS timing model (constants TIMING in the tool; every diagram says so in its notes). Register-indexed families (e.g. MVIB $10-$17 = R0-R7) are drawn once, for R2 (R0 is the PC and would show it being overwritten). .json = WaveDrom source, .svg = picture.
| Opcode | Mnemonic | Operands | Bytes | Microcode steps | Diagram |
|---|---|---|---|---|---|
| $00 | START | 4 | START | ||
| $01 | ON | 1 | 5 | ON | |
| $02 | OFF | 1 | 5 | OFF | |
| $03 | HALT | 1 | 5 | HALT | |
| $04 | JSR | addr | 3 | 28 | JSR |
| $05 | RET | 1 | 17 | RET | |
| $06 | JSRUR | Rn | 2 | 30 | JSRUR |
| $07 | PUSHR | Rn | 2 | 26 | PUSHR |
| $08 | POPR | Rn | 2 | 10 | POPR |
| $09 | PUSH | 1 | 12 | PUSH | |
| $0A | POP | 1 | 10 | POP | |
| $0B | MVAT | 1 | 7 | MVAT | |
| $0C | MVTA | 1 | 8 | MVTA | |
| $0D | LDTI | byte | 2 | 9 | LDTI |
| $0E | LDAI | byte | 2 | 10 | LDAI |
| $0F | MOVRR | Rn,Rn | 2 | 14 | MOVRR |
| $10 | MVIB | Rn,byte | 2 | 10 | MVIB |
| $18 | MVIW | Rn,addr | 3 | 15 | MVIW |
| $20 | MVRLA | Rn | 1 | 8 | MVRLA |
| $28 | MVRHA | Rn | 1 | 8 | MVRHA |
| $30 | MVARL | Rn | 1 | 9 | MVARL |
| $38 | MVARH | Rn | 1 | 9 | MVARH |
| $40 | LDAVR | Rn | 1 | 8 | LDAVR |
| $48 | STAVR | Rn | 1 | 9 | STAVR |
| $50 | INCR | Rn | 1 | 6 | INCR |
| $58 | DECR | Rn | 1 | 7 | DECR |
| $60 | OUTA | Pn | 1 | 9 | OUTA |
| $70 | OUTI | Pn,byte | 2 | 10 | OUTI |
| $80 | LDZ | Rn,byte | 2 | 26 | LDZ |
| $88 | STZ | Rn,byte | 2 | 27 | STZ |
| $90 | INP | Pn | 1 | 9 | INP |
| $A0 | BR | addr | 3 | 18 | BR |
| $A1 | BRZ | addr | 3 | 18 | BRZ |
| $A2 | BRNZ | addr | 3 | 18 | BRNZ |
| $A3 | BRINH | addr | 3 | 18 | BRINH |
| $A4 | BRINL | addr | 3 | 18 | BRINL |
| $A5 | BRNC | undefined: HALT's record | |||
| $A6 | BRC | addr | 3 | 18 | BRC |
| $A7 | BRLT | addr | 3 | 18 | BRLT |
| $A8 | BREQ | addr | 3 | 18 | BREQ |
| $A9 | BRGT | addr | 3 | 18 | BRGT |
| $AA | BRNEQ | addr | 3 | 18 | BRNEQ |
| $AB | BR16Z | addr | 3 | 18 | BR16Z |
| $AC | BR16NZ | addr | 3 | 18 | BR16NZ |
| $AD | BRUR | Rn | 2 | 18 | BRUR |
| $AF | BRDEV | addr | 3 | 18 | BRDEV |
| $B0 | ADDI | byte | 2 | 12 | ADDI |
| $B1 | SUBI | byte | 2 | 12 | SUBI |
| $B2 | ORI | byte | 2 | 10 | ORI |
| $B3 | ANDI | byte | 2 | 10 | ANDI |
| $B4 | XORI | byte | 2 | 10 | XORI |
| $B5 | INVA | 1 | 7 | INVA | |
| $B6 | SHL | 1 | 13 | SHL | |
| $B7 | SHR | 1 | 13 | SHR | |
| $B8 | ADDT | 1 | 10 | ADDT | |
| $B9 | SUBT | 1 | 10 | SUBT | |
| $BA | ORT | 1 | 8 | ORT | |
| $BB | ANDT | 1 | 8 | ANDT | |
| $BC | XORT | 1 | 8 | XORT | |
| $BD | RSHL | 1 | 12 | RSHL | |
| $BE | RSHR | 1 | 13 | RSHR | |
| $BF | PSHR | 1 | 13 | PSHR | |
| $C0 | ADDIW | Rn,addr | 3 | 43 | ADDIW |
| $C8 | SHL16 | Rn | 1 | 33 | SHL16 |
| $D0 | LDIVR | Rn,byte | 2 | 11 | LDIVR |
| $D8 | BRVR | Rn | 1 | 18 | BRVR |
| $E0 | CSHL | 1 | 13 | CSHL | |
| $E1 | CSHR | 1 | 13 | CSHR | |
| $E2 | ADDIC | byte | 2 | 12 | ADDIC |
| $E3 | ADDTC | 1 | 10 | ADDTC | |
| $E4 | LDA | addr | 3 | 18 | LDA |
| $E5 | STA | addr | 3 | 19 | STA |
| $E6 | LDT | addr | 3 | 17 | LDT |
| $E7 | STT | addr | 3 | 17 | STT |
| $E8 | STR | Rn,addr | 3 | 28 | STR |
| $F0 | LDR | Rn,addr | 3 | 26 | LDR |
| $FB | INTE | 1 | 6 | INTE | |
| $FC | INTD | 1 | 6 | INTD | |
| $FD | IRET | 1 | 19 | IRET | |
| $FE | IADDR | addr | 3 | 13 | IADDR |
| $FF | INT | 26 | INT |